Semiconductor manufacturing technologies continue to evolve to provide memory devices having increasingly higher storage capacity, integration density, and response speed. Dynamic random access memory (DRAM) devices are most widely used as memory for electric and electronic apparatuses because such devices can have high storage capacity and integration density. A DRAM device memory cell typically includes one access transistor and one storage capacitor.
As the integration density of a DRAM device memory cell increases, the memory cell generally occupies less area on a semiconductor substrate. With less area, capacitors in the memory cells generally need improved capacitance characteristics.
The capacitance of a capacitor is increased either by using a dielectric layer of a dielectric material that has a higher dielectric constant, or the surface area of the capacitor can be increased. Some high dielectric materials that have been considered for use include Al203, Ta205, or Hf02. However, forming a capacitor with a material of high dielectric constant is complex because of process variations that occur during manufacturing.
To increase the surface area of a capacitor, stacked, trench, and cylindrical type capacitors have been substituted for planar type capacitors.
In the DRAM device, the capacitors are electrically connected to source/drain regions of a semiconductor substrate. Consequently, the locations of the capacitors are limited by the locations of these source/drain regions. When the spacing between adjacent capacitors becomes narrow, an electrical short between capacitors may occur more frequently.
To overcome the above-mentioned problems, a conventional method that is capable of ensuring an overlap margin is used. In this conventional method, storage node electrodes have an effective area regardless of the locations of drains, and are sufficiently spaced apart from each other by expanding an upper portion of a storage node contact plug.
FIGS. 1 and 2 are cross-sectional views illustrating a conventional DRAM device that includes a storage node contact plug having an expanded upper portion. FIG. 1 is a cross-sectional view taken along a line substantially parallel to a word line structure of the DRAM device and FIG. 2 is a cross-sectional view taken along a line substantially parallel to a bit line structure of the DRAM device.
Referring to FIGS. 1 and 2, isolation layers 12 for defining an active region 14 are formed in a semiconductor substrate 10. A word line structure 16 is formed on the semiconductor substrate 10. The word line structure 16 includes a gate insulation layer pattern, a gate electrode pattern and a hard mask pattern sequentially stacked.
Source/drain regions (not shown) are formed in the active region 14 at both sides of the word line structure 16. Generally, the source region is electrically connected to a bit line structure 30 and the drain region is electrically connected to a storage node electrode 38.
A first insulating interlayer 18 covers the word line structure 16. First and second contact pads 20a and 20b electrically connected to the source/drain regions, respectively, are formed at both sides of the word line structure 16.
A second insulating interlayer 22 is formed on the first insulating interlayer 18. A bit line contact (not shown) electrically connected to the first contact pad 20a is formed through the second insulating interlayer 22.
The bit line structure 30 is formed on the second insulating interlayer 22. The bit line structure 30 includes a barrier metal layer pattern 24, a tungsten layer pattern 26 and a capping layer pattern 28, sequentially stacked. A lower face of the barrier metal layer pattern 24 partially makes contact with the bit line contact. Thus, the barrier metal layer pattern 24 is electrically connected to the source region via the bit line contact.
An insulation layer structure 36 covers the bit line structure 30. The insulation layer structure 36 includes a third insulating interlayer 32 and an etching stop layer 34. The storage node contact plug 38 is electrically connected to the first contact pad 20a through the insulation layer structure 36 and the second insulating interlayer 22. The storage node contact plug 38 has a rounded upper portion, resulting in a rounded Y-shape upper portion. A storage node electrode 40 is formed on the storage node contact plug 38.
The storage node electrode 40 may have a sufficient overlap margin with respect to the storage node contact plug 38. Also, shorts between the storage node electrodes 40 may be decreased.
However, while forming the storage node contact plug 38, which fills a storage node contact hole, the storage node contact plug 38 is excessively planarized due to its rounded upper side profile.
Also, the storage node contact plugs 38 generally have widths A different from each other due to polished amounts of the planarization process, again, because of the rounded upper side profile. In particular, when the storage node contact plug 38 has a narrow width A, the overlap margin between the storage node electrode 40 and the storage node contact plug 38 is reduced.
Further, to form the rounded upper portion of the storage node contact hole, the insulation layer structure 36 and the second insulating interlayer 22 are anisotropically etched by a dry etching process and are then isotropically etched by a wet etching process. However, it is very difficult to establish recipes of the wet etching process for preventing adjacent storage contact holes from being in communication with each other and the bit line structure 30 from being exposed.